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ARM: 9474/1: io: avoid KASAN instrumentation of raw halfword I/O
commitd59ed80371upstream. For CPUs before ARMv6, __raw_readw() and __raw_writew() are implemented as C volatile halfword accesses so the compiler can generate an access sequence that is safe for those machines. With KASAN enabled, those C accesses are instrumented as normal memory accesses. That is not valid for MMIO. On ARM926/VersatilePB with KASAN enabled, PL011 probing traps in __asan_store2() while registering the UART, because the instrumented writew() tries to check KASAN shadow for an MMIO address. Keep the existing volatile halfword access, but move the ARMv5 definitions into __no_kasan_or_inline functions so raw MMIO halfword accesses are not instrumented by KASAN. The ARMv6-and-newer inline assembly path is unchanged. Fixes:421015713b("ARM: 9017/2: Enable KASan for ARM") Cc: stable@vger.kernel.org # v5.11+ Signed-off-by: Karl Mehltretter <kmehltretter@gmail.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Greg Kroah-Hartman
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c35c0763af
commit
b6290cc96d
@@ -56,8 +56,19 @@ void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen);
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* the bus. Rather than special-case the machine, just let the compiler
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* generate the access for CPUs prior to ARMv6.
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*/
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#define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
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#define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
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#define __raw_writew __raw_writew
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static __no_kasan_or_inline void __raw_writew(u16 val, volatile void __iomem *addr)
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{
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__chk_io_ptr(addr);
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*(volatile unsigned short __force *)addr = val;
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}
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#define __raw_readw __raw_readw
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static __no_kasan_or_inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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__chk_io_ptr(addr);
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return *(const volatile unsigned short __force *)addr;
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}
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#else
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/*
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* When running under a hypervisor, we want to avoid I/O accesses with
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