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drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDI

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To enable pll clock on DDI move part of the pll enabling
sequence into a ddi clock enabling function.

Simililarly, do the same for pll disabling sequence.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251117104602.2363671-30-mika.kahola@intel.com
This commit is contained in:
Mika Kahola
2025-11-19 13:32:26 +02:00
parent b800af732c
commit e32518d012
5 changed files with 64 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/i915/display/intel_cx0_phy.c
+23 -11
View File
@@ -3280,7 +3280,6 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
* Frequency Change. We handle this step in bxt_set_cdclk().
*/
/* TODO: enable TBT-ALT mode */
intel_cx0_phy_transaction_end(encoder, wakeref);
}
@@ -3346,8 +3345,7 @@ static int intel_mtl_tbt_clock_select(struct intel_display *display,
}
}
void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder, int port_clock)
{
struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
@@ -3361,7 +3359,7 @@ void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
mask = XELPDP_DDI_CLOCK_SELECT_MASK(display);
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
intel_mtl_tbt_clock_select(display, crtc_state->port_clock));
intel_mtl_tbt_clock_select(display, port_clock));
mask |= XELPDP_FORWARD_CLOCK_UNGATE;
val |= XELPDP_FORWARD_CLOCK_UNGATE;
@@ -3399,18 +3397,26 @@ void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
* clock frequency.
*/
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
crtc_state->port_clock);
port_clock);
}
void intel_mtl_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
intel_cx0pll_enable(encoder, &dpll_hw_state->cx0pll);
}
void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
if (intel_tc_port_in_tbt_alt_mode(dig_port))
intel_mtl_tbt_pll_enable(encoder, crtc_state);
intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
else
intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll);
/* TODO: remove when PLL mgr is in place. */
intel_mtl_pll_enable(encoder, NULL, &crtc_state->dpll_hw_state);
}
/*
@@ -3525,7 +3531,7 @@ static bool intel_cx0_pll_is_enabled(struct intel_encoder *encoder)
intel_cx0_get_pclk_pll_request(lane);
}
void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
@@ -3564,13 +3570,19 @@ void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
}
void intel_mtl_pll_disable(struct intel_encoder *encoder)
{
intel_cx0pll_disable(encoder);
}
void intel_mtl_pll_disable_clock(struct intel_encoder *encoder)
{
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
if (intel_tc_port_in_tbt_alt_mode(dig_port))
intel_mtl_tbt_pll_disable(encoder);
intel_mtl_tbt_pll_disable_clock(encoder);
else
intel_cx0pll_disable(encoder);
/* TODO: remove when PLL mgr is in place. */
intel_mtl_pll_disable(encoder);
}
enum icl_port_dpll_id
drivers/gpu/drm/i915/display/intel_cx0_phy.h
+10 -1
View File
@@ -20,6 +20,7 @@ struct intel_crtc;
struct intel_crtc_state;
struct intel_cx0pll_state;
struct intel_display;
struct intel_dpll;
struct intel_dpll_hw_state;
struct intel_encoder;
struct intel_hdmi;
@@ -28,11 +29,19 @@ void intel_clear_response_ready_flag(struct intel_encoder *encoder,
int lane);
bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
void intel_mtl_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
void intel_mtl_pll_disable(struct intel_encoder *encoder);
enum icl_port_dpll_id
intel_mtl_port_pll_type(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_mtl_pll_disable_clock(struct intel_encoder *encoder);
void intel_mtl_pll_disable_clock(struct intel_encoder *encoder);
void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder,
int port_clock);
void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder);
int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder,
drivers/gpu/drm/i915/display/intel_ddi.c
+4 -2
View File
@@ -89,6 +89,8 @@
#include "skl_scaler.h"
#include "skl_universal_plane.h"
struct intel_dpll;
static const u8 index_to_dp_signal_levels[] = {
[0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
@@ -5252,8 +5254,8 @@ void intel_ddi_init(struct intel_display *display,
encoder->port_pll_type = intel_mtl_port_pll_type;
encoder->get_config = xe3plpd_ddi_get_config;
} else if (DISPLAY_VER(display) >= 14) {
encoder->enable_clock = intel_mtl_pll_enable;
encoder->disable_clock = intel_mtl_pll_disable;
encoder->enable_clock = intel_mtl_pll_enable_clock;
encoder->disable_clock = intel_mtl_pll_disable_clock;
encoder->port_pll_type = intel_mtl_port_pll_type;
encoder->get_config = mtl_ddi_get_config;
} else if (display->platform.dg2) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+25
View File
@@ -4391,7 +4391,32 @@ static int mtl_pll_get_freq(struct intel_display *display,
return intel_cx0pll_calc_port_clock(encoder, &dpll_hw_state->cx0pll);
}
static void mtl_pll_enable(struct intel_display *display,
struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
struct intel_encoder *encoder = get_intel_encoder(display, pll);
if (drm_WARN_ON(display->drm, !encoder))
return;
intel_mtl_pll_enable(encoder, pll, dpll_hw_state);
}
static void mtl_pll_disable(struct intel_display *display,
struct intel_dpll *pll)
{
struct intel_encoder *encoder = get_intel_encoder(display, pll);
if (drm_WARN_ON(display->drm, !encoder))
return;
intel_mtl_pll_disable(encoder);
}
static const struct intel_dpll_funcs mtl_pll_funcs = {
.enable = mtl_pll_enable,
.disable = mtl_pll_disable,
.get_hw_state = mtl_pll_get_hw_state,
.get_freq = mtl_pll_get_freq,
};
drivers/gpu/drm/i915/display/intel_lt_phy.c
+2 -2
View File
@@ -2310,7 +2310,7 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
if (intel_tc_port_in_tbt_alt_mode(dig_port))
intel_mtl_tbt_pll_enable(encoder, crtc_state);
intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
else
intel_lt_phy_pll_enable(encoder, crtc_state);
}
@@ -2320,7 +2320,7 @@ void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
if (intel_tc_port_in_tbt_alt_mode(dig_port))
intel_mtl_tbt_pll_disable(encoder);
intel_mtl_tbt_pll_disable_clock(encoder);
else
intel_lt_phy_pll_disable(encoder);