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drm/amd/display: Temp disable repeater FGCG as workaround

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[why & how]
There is an issue that is seemingly limited to DCN42 where systems with
IOMMU enabled will hang during reboot stress testing. The hang happens shortly
after DCN PG exit happens and HUBP is programmed for the first flip, but before
the first surface address is latched. Testing has shown that disabling
DCCG_GLOBAL_FGCG_REP_DIS, HUBP_FGCG_REP_DIS, and DCFCLK_GATE_DIS can mask this
issue.

Disable FGCG for these three repeater bits to avoid issue while debug is on-going.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ovidiu Bunea
2026-06-17 16:08:44 -04:00
committed by Alex Deucher
parent 0fde96e06f
commit ec9b4b2629
5 changed files with 21 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/amd/display/dc/dc.h
+1
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@@ -1288,6 +1288,7 @@ struct dc_debug_options {
unsigned int min_deep_sleep_dcfclk_khz;
unsigned int force_odm2to1_for_edp_pixclk_mhz;
bool enable_replay_esd_recovery;
uint8_t iommu_mismatch_temp_wka;
};
drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c
+5 -1
View File
@@ -81,8 +81,12 @@ void dccg42_enable_global_fgcg(struct dccg *dccg, bool value)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
if (dccg->ctx->dc->debug.disable_clock_gate)
/* Temporary workaround for IOMMU mismatch issue.
* Fine grain control via bit2 of debug flag.
*/
if (dccg->ctx->dc->debug.disable_clock_gate || (dccg->ctx->dc->debug.iommu_mismatch_temp_wka & 0x4))
value = false;
REG_UPDATE(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, !value);
}
drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
+6
View File
@@ -20,6 +20,12 @@ static void hubp42_set_fgcg(struct hubp *hubp, bool enable)
{
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
/* Temporary workaround for IOMMU mismatch issue.
* Fine grain control via bit1 of debug flag.
*/
if (hubp->ctx->dc->debug.iommu_mismatch_temp_wka & 0x2)
enable = false;
REG_UPDATE(HUBP_CLK_CNTL, HUBP_FGCG_REP_DIS, !enable);
}
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
+8 -1
View File
@@ -70,6 +70,7 @@ void dcn42_init_hw(struct dc *dc)
uint32_t user_level = MAX_BACKLIGHT_LEVEL;
bool dchub_ref_freq_changed;
int current_dchub_ref_freq = 0;
uint8_t dcfclk_gate_dis_value = 0;
if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks) {
dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
@@ -243,7 +244,13 @@ void dcn42_init_hw(struct dc *dc)
/* enable all DCN clock gating */
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
/* Temporary workaround for IOMMU mismatch issue.
* Fine grain control via bit0 of debug flag.
*/
if (dc->debug.iommu_mismatch_temp_wka & 0x1)
dcfclk_gate_dis_value = 1;
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, dcfclk_gate_dis_value);
}
dcn401_setup_hpo_hw_control(hws, true);
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
+1
View File
@@ -801,6 +801,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.replay_skip_crtc_disabled = true,
.psr_skip_crtc_disable = true,
.force_odm2to1_for_edp_pixclk_mhz = 0, // disable the policy for now
.iommu_mismatch_temp_wka = 0x7,
};
static const struct dc_check_config config_defaults = {