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Dmitry Baryshkov 46ea59235c arm64: dts: qcom: pm4125: define USB-C related blocks 
Define VBUS regulator and the Type-C handling block as present on the
Quacomm PM4125 PMIC.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20240202-pm4125-typec-v2-3-12771d85700d@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-16 18:00:43 -06:00
Lucas Karpinski 07bbe3fd07 arm64: dts: qcom: sa8540p-ride: disable pcie2a node 
pcie2a and pcie3a both cause interrupt storms to occur. However, when
both are enabled simultaneously, the two combined interrupt storms will
lead to rcu stalls. Red Hat is the only company still using this board
and since we still need pcie3a, just disable pcie2a.

Signed-off-by: Lucas Karpinski <lkarpins@redhat.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/qcoqksikfvdqxk6stezbzc7l2br37ccgqswztzqejmhrkhbrwt@ta4npsm35mqk
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-16 17:52:58 -06:00
Viken Dadhaniya 498006fd49 arm64: dts: qcom: sc7280: add slimbus DT node 
Populate the DTSI node for slimbus instance to be
used by bluetooth FM audio case.

Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>
Link: https://lore.kernel.org/r/20240215090910.30021-1-quic_vdadhani@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-16 17:12:48 -06:00
Ankit Sharma 942bf463de arm64: dts: qcom: sc7280: Add capacity and DPC properties 
The "capacity-dmips-mhz" and "dynamic-power-coefficient" are
used to build Energy Model which in turn is used by EAS to take
placement decisions. So add it to SC7280 soc.

Signed-off-by: Ankit Sharma <quic_anshar@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231103105440.23904-1-quic_anshar@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-16 15:32:52 -06:00
Luca Weiss dc14578426 arm64: dts: qcom: pmi632: Add PBS client and use in LPG node 
With SDAM + PBS the LPG driver can configure the LED pattern in
hardware.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20240205-pmi632-ppg-v1-2-e236c95a2099@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-16 14:32:37 -06:00
Neil Armstrong 114990ce3e arm64: dts: qcom: sm8550: Use GIC-ITS for PCIe0 and PCIe1 
Both PCIe0 and PCIe1 controllers are capable of signalling the MSIs
received from endpoint devices to the CPU using GIC-ITS MSI controller.
Add support for it.

The GIC-ITS MSI implementation provides an advantage over internal MSI
implementation using Locality-specific Peripheral Interrupts (LPI) that
would allow MSIs to be targeted for each CPU core.

Like SM8450, the IDs are swapped, but works fine on PCIe0 and PCIe1.

WiFi PCIe Device on SM8550-QRD using GIC-ITS:
218:          0          4          0          0          0          0          0          0   ITS-MSI 524288 Edge      bhi
219:          0          0          5          0          0          0          0          0   ITS-MSI 524289 Edge      mhi
220:          0          0          0         33          0          0          0          0   ITS-MSI 524290 Edge      mhi
221:          0          0          0          0          3          0          0          0   ITS-MSI 524291 Edge      ce0
222:          0          0          0          0          0          1          0          0   ITS-MSI 524292 Edge      ce1
223:          0          0          0          0          0          0         38          0   ITS-MSI 524293 Edge      ce2
224:          0          0          0          0          0          0          0         31   ITS-MSI 524294 Edge      ce3
225:          0          0          0          0          0          0          0          0   ITS-MSI 524295 Edge      ce5
226:          0          0          0          0          0          0          0          0   ITS-MSI 524296 Edge      DP_EXT_IRQ
227:          0          0          0          0          0          0          0          0   ITS-MSI 524297 Edge      DP_EXT_IRQ
228:          0          0          0          0          0          0          0          0   ITS-MSI 524298 Edge      DP_EXT_IRQ
229:          0          0          0          0          0          0          0          0   ITS-MSI 524299 Edge      DP_EXT_IRQ
230:          0          0          0          0          0          0          0          0   ITS-MSI 524300 Edge      DP_EXT_IRQ
231:          0          0          0          0          0          0          0          0   ITS-MSI 524301 Edge      DP_EXT_IRQ
232:          0          0          0          0          0          0          0          0   ITS-MSI 524302 Edge      DP_EXT_IRQ

NVMe in SM8550-HDK M.2 Slot using GIC-ITS:
212:          0          0         22          0          0          0          0          0   ITS-MSI 134742016 Edge      nvme0q0
213:     133098          0          0          0          0          0          0          0   ITS-MSI 134742017 Edge      nvme0q1
214:          0     139450          0          0          0          0          0          0   ITS-MSI 134742018 Edge      nvme0q2
215:          0          0     139476          0          0          0          0          0   ITS-MSI 134742019 Edge      nvme0q3
216:          0          0          0      69767          0          0          0          0   ITS-MSI 134742020 Edge      nvme0q4
217:          0          0          0          0      80368          0          0          0   ITS-MSI 134742021 Edge      nvme0q5
218:          0          0          0          0          0      77315          0          0   ITS-MSI 134742022 Edge      nvme0q6
219:          0          0          0          0          0          0      73022          0   ITS-MSI 134742023 Edge      nvme0q7
220:          0          0          0          0          0          0          0     329993   ITS-MSI 134742024 Edge      nvme0q8

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240122-topic-sm8550-upstream-pcie-its-v2-1-b3398d86d1f1@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-16 12:42:02 -06:00
Krzysztof Kozlowski 7c38989d0f arm64: dts: qcom: sm8150: correct PCIe wake-gpios 
Bindings allow a "wake", not "enable", GPIO.  Schematics also use WAKE
name for the pin:

  sa8155p-adp.dtb: pcie@1c00000: Unevaluated properties are not allowed ('enable-gpio' was unexpected)

Fixes: a1c86c6805 ("arm64: dts: qcom: sm8150: Add PCIe nodes")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240108131216.53867-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-16 12:09:54 -06:00
Krzysztof Kozlowski 584a327c5c arm64: dts: qcom: sdm845-db845c: correct PCIe wake-gpios 
Bindings allow a "wake", not "enable", GPIO.  Schematics also use WAKE
name for the pin:

  sdm845-db845c.dtb: pcie@1c00000: Unevaluated properties are not allowed ('enable-gpio' was unexpected)

Fixes: 4a657c264b ("arm64: dts: qcom: db845c: Enable PCIe controllers")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240108131216.53867-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-16 12:09:54 -06:00
Luca Weiss 891af1aa1e arm64: dts: qcom: sm7225-fairphone-fp4: Enable display and GPU 
Add the description for the display panel found on this phone.
Unfortunately the LCDB module on PM6150L isn't yet supported upstream so
we need to use a dummy regulator-fixed in the meantime.

And with this done we can also enable the GPU and set the zap shader
firmware path.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20240216-fp4-panel-v3-4-a556e4b79640@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-16 11:18:49 -06:00
Luca Weiss 2abe4a310c arm64: dts: qcom: sm6350: Remove "disabled" state of GMU 
The GMU won't probe without GPU being enabled, so we can remove the
disabled status so we don't have to explicitly enable the GMU in all the
devices that enable GPU.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20240216-fp4-panel-v3-3-a556e4b79640@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-16 11:18:32 -06:00
Joe Mason b61fbc595e arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add fuel gauge 
Like the Samsung Galaxy A3/A5, the Grand Prime/Core Prime uses a
Richtek RT5033 PMIC as battery fuel gauge, charger, flash LED and for some
regulators.
For now, only add the fuel gauge/battery device to the device tree, so we
can check the remaining battery percentage.

The other RT5033 drivers need some more work first before they can be used
properly.

Signed-off-by: Joe Mason <buddyjojo06@outlook.com>
[Raymond: Move to fortuna-common. Use interrupts-extended]
Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240216124639.24689-1-raymondhackley@protonmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-16 11:16:43 -06:00
Luca Weiss fc48bb3135 arm64: dts: qcom: sm6350: Add interconnect for MDSS 
Add the definition for the interconnect used in the display subsystem.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240216-sm6350-interconnect-v1-1-9d55667c06ca@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-16 11:16:37 -06:00
Walter Broemeling e1839f78e4 arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add initial device trees 
Samsung Galaxy Core Prime and Grand Prime are phones based on MSM8916.
They are similar to the other Samsung devices based on MSM8916 with only a
few minor differences.

This initial commit adds support for:
 - fortuna3g (SM-G530H)
 - gprimeltecan (SM-G530W)
 - grandprimelte (SM-G530FZ)
 - rossa (SM-G360G)

The device trees contain initial support with:
 - GPIO keys
 - Regulator haptic
 - SDHCI (internal and external storage)
 - USB Device Mode
 - UART (on USB connector via the SM5502/SM5504 MUIC)
 - WCNSS (WiFi/BT)
 - Regulators
 - QDSP6 audio
 - Speaker/earpiece/headphones/microphones via digital/analog codec in
   MSM8916/PM8916
 - WWAN Internet via BAM-DMUX

There are different variants of Core Prime and Grand Prime, with some
differences in accelerometer, NFC and panel.
Core Prime and Grand Prime are similar, with some differences in MUIC,
panel and touchscreen.

The common parts are shared in
msm8916-samsung-fortuna-common.dtsi and msm8916-samsung-rossa-common.dtsi
to reduce duplication.

Signed-off-by: Walter Broemeling <wallebroem@gmail.com>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
[Joe: Add audio, buttons and WiFi]
Signed-off-by: Joe Mason <buddyjojo06@outlook.com>
[Siddharth: Add fortuna3g]
Signed-off-by: Siddharth Manthan <siddharth.manthan@gmail.com>
[Raymond: Add modem, fortuna-common.dtsi, grandprimelte and rossa]
Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com>
Link: https://lore.kernel.org/r/20240129143147.5058-1-raymondhackley@protonmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-14 09:41:27 -06:00
Konrad Dybcio 2f7be4caac arm64: dts: qcom: sm8550: Switch UFS from opp-table-hz to opp-v2 
Now that the non-legacy form of OPP is supported within the UFS driver,
go ahead and switch to it, adding support for more intermediate freq/power
states.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Link: https://lore.kernel.org/r/20240203-topic-8550_ufs_oppv2-v2-1-b0bef2a73e6c@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-14 09:41:27 -06:00
Krzysztof Kozlowski 1587bb53c1 arm64: dts: qcom: sc8180x: describe all PCI MSI interrupts 
Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts.  This
also corrects PCIe1 and PCIe2 first MSI interrupt.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240205163123.81842-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-14 09:41:27 -06:00
Krzysztof Kozlowski 77e7257a60 arm64: dts: qcom: minor whitespace cleanup 
The DTS code coding style expects exactly one space before '{' and
around '=' characters.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240208105208.128706-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-14 09:41:27 -06:00
Krzysztof Kozlowski 1fe82781df arm64: dts: qcom: ssm7125-xiaomi: drop incorrect UFS phy max current 
Neither bindings nor UFS phy driver use properties like
'vdda-phy-max-microamp' and 'vdda-pll-max-microamp':

  sm7125-xiaomi-curtana.dtb: phy@1d87000: 'vdda-phy-max-microamp', 'vdda-pll-max-microamp' do not match any of the regexes: 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240212150558.81896-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-14 09:41:27 -06:00
Krzysztof Kozlowski 4442a67eed arm64: dts: qcom: x1e80100-crd: add sound card 
Add sound card to X1E80100-CRD board and update DMIC supply.  Works so
far:
 - Audio playback via speakers or audio jack headset,
 - DMIC0-3 recording.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240212184403.246299-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-14 09:41:27 -06:00
Krzysztof Kozlowski 8794916799 arm64: dts: x1e80100: correct DMIC2 and DMIC3 pin config node names 
Correct the TLMM pin configuration and muxing node names used for DMIC2
and DMIC3 (dmic01 -> dmic23).  This has no functional impact, but
improves code readability and avoids any confusion when reading the DTS.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240212172335.124845-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-14 09:41:20 -06:00
Krzysztof Kozlowski 94c3127671 arm64: dts: sm8650: correct DMIC2 and DMIC3 pin config node names 
Correct the TLMM pin configuration and muxing node names used for DMIC2
and DMIC3 (dmic01 -> dmic23).  This has no functional impact, but
improves code readability and avoids any confusion when reading the DTS.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240212172335.124845-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-14 09:41:20 -06:00
Krzysztof Kozlowski c6e5bf9278 arm64: dts: sm8550: correct DMIC2 and DMIC3 pin config node names 
Correct the TLMM pin configuration and muxing node names used for DMIC2
and DMIC3 (dmic01 -> dmic23).  This has no functional impact, but
improves code readability and avoids any confusion when reading the DTS.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240212172335.124845-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-14 09:41:19 -06:00
Krzysztof Kozlowski 0d3eb7ff1f arm64: dts: sm8450: correct DMIC2 and DMIC3 pin config node names 
Correct the TLMM pin configuration and muxing node names used for DMIC2
and DMIC3 (dmic01 -> dmic23).  This has no functional impact, but
improves code readability and avoids any confusion when reading the DTS.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240212172335.124845-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-14 09:41:19 -06:00
Krzysztof Kozlowski 61474b18e7 arm64: dts: sc8280xp: correct DMIC2 and DMIC3 pin config node names 
Correct the TLMM pin configuration and muxing node names used for DMIC2
and DMIC3 (dmic01 -> dmic23).  This has no functional impact, but
improves code readability and avoids any confusion when reading the DTS.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240212172335.124845-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-14 09:41:19 -06:00
Mark Hasemeyer a7baa25bfb arm64: dts: qcom: sdm845: Enable cros-ec-spi as wake source 
The cros_ec driver currently assumes that cros-ec-spi compatible device
nodes are a wakeup-source even though the wakeup-source property is not
defined.

Some Chromebooks use a separate wake pin, while others overload the
interrupt for wake and IO. With the current assumption, spurious wakes
can occur on systems that use a separate wake pin. It is planned to
update the driver to no longer assume that the EC interrupt pin should
be enabled for wake.

Add the wakeup-source property to all cros-ec-spi compatible device
nodes to signify to the driver that they should still be a valid wakeup
source.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Mark Hasemeyer <markhas@chromium.org>
Link: https://lore.kernel.org/r/20240102140734.v4.16.I870e2c3490e7fc27a8f6bc41dba23b3dfacd2d13@changeid
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-13 23:37:17 -06:00
Mark Hasemeyer a4b28b9ecc arm64: dts: qcom: sc7280: Enable cros-ec-spi as wake source 
The cros_ec driver currently assumes that cros-ec-spi compatible device
nodes are a wakeup-source even though the wakeup-source property is not
defined.

Some Chromebooks use a separate wake pin, while others overload the
interrupt for wake and IO. With the current assumption, spurious wakes
can occur on systems that use a separate wake pin. It is planned to
update the driver to no longer assume that the EC interrupt pin should
be enabled for wake.

Add the wakeup-source property to all cros-ec-spi compatible device
nodes to signify to the driver that they should still be a valid wakeup
source.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Mark Hasemeyer <markhas@chromium.org>
Link: https://lore.kernel.org/r/20240102140734.v4.15.I7ea3f53272c9b7cd77633adfd18058ba443eed96@changeid
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-13 23:37:17 -06:00
Mark Hasemeyer f172a341ec arm64: dts: qcom: sc7180: Enable cros-ec-spi as wake source 
The cros_ec driver currently assumes that cros-ec-spi compatible device
nodes are a wakeup-source even though the wakeup-source property is not
defined.

Some Chromebooks use a separate wake pin, while others overload the
interrupt for wake and IO. With the current assumption, spurious wakes
can occur on systems that use a separate wake pin. It is planned to
update the driver to no longer assume that the EC interrupt pin should
be enabled for wake.

Add the wakeup-source property to all cros-ec-spi compatible device
nodes to signify to the driver that they should still be a valid wakeup
source.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Mark Hasemeyer <markhas@chromium.org>
Link: https://lore.kernel.org/r/20240102140734.v4.14.I2ee94aede9e25932f656c2bdb832be3199fa1291@changeid
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-13 23:37:17 -06:00
Konrad Dybcio 5dd227ccfb arm64: dts: qcom: sdm845: Use the Low Power Island CX/MX for SLPI 
The SLPI is powered by the Low Power Island power rails. Fix the incorrect
assignment.

Fixes: 74588aada5 ("arm64: dts: qcom: sdm845: add SLPI remoteproc")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231220-topic-sdm845_slpi_lcxmx-v1-1-db7c72ef99ae@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-13 23:33:05 -06:00
Yassine Oudjana 68c4c20848 arm64: dts: qcom: msm8996: Define UFS UniPro clock limits 
These limits were always defined as 0, but that didn't cause any issue
since the driver had hardcoded limits. In commit b4e13e1ae9 ("scsi: ufs:
qcom: Add multiple frequency support for MAX_CORE_CLK_1US_CYCLES") the
hardcoded limits were removed and the driver started reading them from DT,
causing UFS to stop working on MSM8996. Add real UniPro clock limits to fix
UFS.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Fixes: 57fc67ef0d ("arm64: dts: qcom: msm8996: Add ufs related nodes")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231218133917.78770-1-y.oudjana@protonmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-13 23:32:49 -06:00
Bjorn Andersson 7c6bef576a arm64: dts: qcom: qcs6490-rb3gen2: Declare GCC clocks protected 
The SC7280 GCC binding describes clocks which, due to the difference in
security model, are not accessible on the RB3gen2 - in the same way seen
on QCM6490.

Mark these clocks as protected, to allow the board to boot. In contrast
to the present QCM6490 boards GCC_EDP_CLKREF_EN is left out, as this
does not need to be "protected" and is used on the RB3Gen2 board.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20240209-qcm6490-gcc-protected-clocks-v2-1-11cd5fc13bd0@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-13 23:30:19 -06:00
Bjorn Andersson a36a566b53 arm64: dts: qcom: sc8280xp-pmics: Define adc for temp-alarms 
sc8280xp-pmics define the two thermal zones "pm8280-1-thermal" and
"pm8280-2-thermal", but the related temp-alarm instances are not tied to
any adc channels, and as such continuously report the bogus temperature
of 37C.

After previously defining these adc channels across all boards using
sc8280xp-pmics.dtsi, we can now add these references.

This does however mean that we have a non-disabled node referencing
default-disabled nodes, requiring each board to enable the pmk8280_vadc.
Avoid this by marking pmk8280_vadc okay.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240210-sc8280xp-pmic-thermal-v1-2-a1c215a17d10@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-13 23:30:01 -06:00
Bjorn Andersson 6cca740cf3 arm64: dts: qcom: sc8280xp-crd: Add PMIC die-temp vadc channels 
The die-temp vadc channels are not defined for the CRD, but describing
them directly would directly duplicate the definition from the Lenovo
Thinkpad X13s DeviceTree.

The sc8280xp-pmics file describes the common configuration of PMK8280,
two PMC8280, PMC8280C, and PMR735a. As such, even though these vadc
channels makes references across PMICs, it's suitable to define them in
the shared file.

Do this, and enable the pmk8280 vadc for the CRD.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240210-sc8280xp-pmic-thermal-v1-1-a1c215a17d10@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-13 23:30:01 -06:00
Dmitry Baryshkov a06a2f12f9 arm64: dts: qcom: qrb4210-rb2: enable USB-C port handling 
Plug in USB-C related bits and pieces to enable USB role switching and
USB-C orientation handling for the Qualcomm RB2 board.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240130-pmi632-typec-v3-6-b05fe44f0a51@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-09 17:05:59 -06:00
Vladimir Zapolskiy 7e3a1f6470 arm64: dts: qcom: sm6115: drop pipe clock selection 
Stop selecting UTMI clock as the USB3 PIPE clock. This setting is
incompatible with the USB host working in USB3 (SuperSpeed) mode.
While we are at it, also drop the default setting for the port speed.

Fixes: 9dd5f6dba7 ("arm64: dts: qcom: sm6115: Add USB SS qmp phy node")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
[DB: fixed commit message, dropped dr_mode setting]
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Luca Weiss <luca.weiss@fairphone.com> # sdm632-fairphone-fp3
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240130-pmi632-typec-v3-5-b05fe44f0a51@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-09 17:05:42 -06:00
Dmitry Baryshkov f69b3e40f4 arm64: dts: qcom: pmi632: define USB-C related blocks 
Define VBUS regulator and the Type-C handling block as present on the
Quacomm PMI632 PMIC.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Luca Weiss <luca.weiss@fairphone.com> # sdm632-fairphone-fp3
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240130-pmi632-typec-v3-4-b05fe44f0a51@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-09 17:05:41 -06:00
Komal Bajaj 05f439c0e6 arm64: dts: qcom: qcs6490-rb3gen2: Correct the voltage setting for vph_pwr 
Min and max voltages for vph_pwr should be same, otherwise rpmh
will not probe, so correcting the min and max voltages for vph_pwr.

Fixes: 04cf333afc ("arm64: dts: qcom: Add base qcs6490-rb3gen2 board dts")
Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231220110015.25378-3-quic_kbajaj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-09 11:45:49 -06:00
Komal Bajaj aa56130e88 arm64: dts: qcom: qcm6490-idp: Correct the voltage setting for vph_pwr 
Min and max voltages for vph_pwr should be same, otherwise rpmh
will not probe, so correcting the min and max voltages for vph_pwr.

Fixes: 9af6a9f32a ("arm64: dts: qcom: Add base qcm6490 idp board dts")
Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231220110015.25378-2-quic_kbajaj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-09 11:45:49 -06:00
Bjorn Andersson 014bbc990e arm64: dts: qcom: sc8280xp: Introduce additional tsens instances 
The SC8280XP contains two additional tsens instances, providing among
other things thermal measurements for the GPU.

Add these and a GPU thermal-zone.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20240206-sc8280xp-tsens2_3-v3-1-4577b3b38ea8@quicinc.com
[bjorn: s/cpu-crit/gpu-crit/]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 22:42:59 -06:00
Neil Armstrong 31ca6241fe arm64: dts: qcom: sm8550-hdk: correct WCD9385 route and port mapping 
Starting from SM8550, the TX ADC input soundwire port is offset by 1,
and uses the new SWR_INPUTx input ports, so replace the legacy
SWR_ADCx routes for SWR_INPUT0 & SWR_INPUT1 following the correct
TX Soundwire port mapping.

Add some comments on the routing for clarity.

Fixes: b5e25ded27 ("arm64: dts: qcom: sm8550: add support for the SM8550-HDK board")
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240201-topic-sm8550-hdk8550-audio-fix-v1-1-aa526c9c91d5@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 17:54:41 -06:00
Manivannan Sadhasivam 0f9b8054bb arm64: dts: qcom: sm8650: Fix UFS PHY clocks 
QMP PHY used in SM8650 requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from TCSR

Fixes: 10e0246712 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-17-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 17:54:41 -06:00
Manivannan Sadhasivam 746ae23ad0 arm64: dts: qcom: sm8550: Fix UFS PHY clocks 
QMP PHY used in SM8550 requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from TCSR

Fixes: 35cf1aaab1 ("arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes")
Reviewed-by: Can Guo <quic_cang@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-16-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 17:54:41 -06:00
Manivannan Sadhasivam 8edbdefee1 arm64: dts: qcom: sm8350: Fix UFS PHY clocks 
QMP PHY used in SM8350 requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

While at it, let's move 'clocks' property before 'clock-names' to match
the style used commonly.

Fixes: 59c7cf8147 ("arm64: dts: qcom: sm8350: Add UFS nodes")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-15-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 17:54:41 -06:00
Manivannan Sadhasivam 1d4ef9644e arm64: dts: qcom: sc8280xp: Fix UFS PHY clocks 
QMP PHY used in SC8280XP requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

Fixes: 152d1faf1e ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-14-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 17:54:41 -06:00
Manivannan Sadhasivam dde7714022 arm64: dts: qcom: sc8180x: Fix UFS PHY clocks 
QMP PHY used in SC8180X requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

Fixes: 8575f197b0 ("arm64: dts: qcom: Introduce the SC8180x platform")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-13-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 17:54:41 -06:00
Bjorn Andersson cc2bc7a7ab Merge branch '20240131-ufs-phy-clock-v3-3-58a49d2f4605@linaro.org' into HEAD 
Merge clock topic branch that introduces the SC8180X CLK_REF enable
clocks.
 2024-02-06 17:54:05 -06:00
Manivannan Sadhasivam 55ee02b10b arm64: dts: qcom: sm8250: Fix UFS PHY clocks 
QMP PHY used in SM8250 requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

While at it, let's move 'clocks' property before 'clock-names' to match
the style used commonly.

Fixes: b7e2fba066 ("arm64: dts: qcom: sm8250: Add UFS controller and PHY")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-12-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:18:38 -06:00
Manivannan Sadhasivam eff7496b72 arm64: dts: qcom: sm8150: Fix UFS PHY clocks 
QMP PHY used in SM8150 requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

While at it, let's move 'clocks' property before 'clock-names' to match
the style used commonly.

Fixes: 3834a2e922 ("arm64: dts: qcom: sm8150: Add ufs nodes")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-11-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:18:38 -06:00
Manivannan Sadhasivam 68f9fcba3a arm64: dts: qcom: sm6350: Fix UFS PHY clocks 
QMP PHY used in SM6350 requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

While at it, let's move 'clocks' property before 'clock-names' to match
the style used commonly.

Fixes: 5a814af5fc ("arm64: dts: qcom: sm6350: Add UFS nodes")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-10-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:18:38 -06:00
Manivannan Sadhasivam 3823a877f2 arm64: dts: qcom: sm6125: Fix UFS PHY clocks 
QMP PHY used in SM6125 requires 3 clocks:

* ref - 19.2MHz reference clock from RPM
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

Fixes: f8399e8a2f ("arm64: dts: qcom: sm6125: Add UFS nodes")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-9-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:18:38 -06:00
Manivannan Sadhasivam a820a285ef arm64: dts: qcom: sm6115: Fix UFS PHY clocks 
QMP PHY used in SM6115 requires 3 clocks:

* ref - 19.2MHz reference clock from RPM
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

Fixes: 97e563bf5b ("arm64: dts: qcom: sm6115: Add basic soc dtsi")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-8-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:18:38 -06:00
Manivannan Sadhasivam ca8fb2bd22 arm64: dts: qcom: sdm845: Fix UFS PHY clocks 
QMP PHY used in SDM845 requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

While at it, let's move 'clocks' property before 'clock-names' to match
the style used commonly.

Fixes: cc16687fbd ("arm64: dts: qcom: sdm845: add UFS controller")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-7-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:18:38 -06:00