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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Like other architectures such as x86, arm64, riscv, powerpc and s390, select THREAD_INFO_IN_TASK for LoongArch to move thread_info off the stack into task_struct. This follows modern kernel standards and also makes the system more secure. With this patch, thread_info is included in task_struct at an offset of 0 instead of being placed at the bottom of the kernel stack. Thus, the $tp register points to both thread_info and task_struct. To support this, introduce a per-CPU variable cpu_tasks to store the pointer to the current task_struct. This decouples the recovery of the $tp register from the stack pointer during exception entry. Then initialize cpu_tasks for the primary and secondary CPUs during arch-specific setup and SMP boot paths. To eliminate the dangerous windows during the early initialization where the cpu_tasks remains uninitialized, set_current() is invoked as early as possible in both setup_arch() and start_secondary(). This ensures the $tp recovery barrier is armed in case any early boot exceptions or kernel panics occur. Modify SAVE_SOME and handle_syscall to restore the $tp register from cpu_tasks, and also use the la_abs absolute addressing for cpu_tasks access in assembly to bypass the relocation limits within exception handling sections. By advancing the preservation of u0 in SAVE_SOME, we reuse the PERCPU_BASE_KS value in u0 for the cpu_tasks calculation, effectively eliminating a duplicate csrrd instruction execution on SMP platforms. Update <asm/switch_to.h> and <kernel/switch.S> to fully support the CONFIG_THREAD_INFO_IN_TASK feature. Remove the obsolete next_ti argument from __switch_to(), which shifts the remaining arguments ahead in the calling convention (sched_ra from a3 to a2, and sched_cfa from a4 to a3). Under the new configuration, __switch_to() now directly derives the thread pointer ($tp) from the next task_struct pointer in a1. To preserve the optimal and clean "move tp, a1" path for 64-bit kernels, the thread pointer ($tp) is assigned directly from a1 in the core path. For 32-bit kernels, where a1 carries a 2000-byte structural pointer bias at entry, an explicit adjustment "PTR_ADDI tp, tp, -TASK_STRUCT_OFFSET" is introduced at the function exit. In the context of __switch_to(), local interrupts are disabled, and the kernel is in a critical switching phase where handling any synchronous exception is practically impossible and prohibited. If any synchronous exception or watchpoint does trigger in this narrow window, it constitutes a fatal double fault and the kernel is expected to die/panic immediately anyway. Therefore, the temporary biased value in $tp is safe and acceptable here. Additionally, evaluate the stack lookup as a single load instruction "LONG_LPTR t0, a1, (TASK_STACK - TASK_STRUCT_OFFSET)", this perfectly satisfies both 32-bit and 64-bit kernels. Using the "next" pointer in a1 as the base register, rather than $tp, effectively unchains the data dependency (RAW hazard) from the preceding move instruction, maximizing the instruction-level parallelism and superscalar execution efficiency while naturally adapting the structural shift. With CONFIG_THREAD_INFO_IN_TASK enabled, the kernel stack life cycle is decoupled from task_struct and can be freed concurrently. Currently, show_stacktrace() reads raw stack data via __get_addr() and subsequently calls show_backtrace() to unwind the frame, without holding any reference to the target task's stack. If show_stacktrace() is called on a concurrently exiting task, it could attempt to read from a freed or reallocated kernel stack. This introduces a severe use-after-free (UAF) read risk or kernel panics. Wrap the entire stack inspection process inside show_stacktrace() with a try_get_task_stack() and put_task_stack() pair. This ensures the task stack remains pinned safely during both the raw stack data dump loop and the subsequent stack unwinding phase. Also, ensure that the task pointer is initialized to "current" early if it is NULL, so that try_get_task_stack() always operates on a valid task reference. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
277 lines
6.1 KiB
C
277 lines
6.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_STACKFRAME_H
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#define _ASM_STACKFRAME_H
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#include <linux/threads.h>
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/asm-offsets.h>
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#include <asm/loongarch.h>
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#include <asm/thread_info.h>
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#include <asm/unwind_hints.h>
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/* Make the addition of cfi info a little easier. */
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.macro cfi_rel_offset reg offset=0 docfi=0
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.if \docfi
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.cfi_rel_offset \reg, \offset
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.endif
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.endm
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.macro cfi_st reg offset=0 docfi=0
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cfi_rel_offset \reg, \offset, \docfi
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LONG_S \reg, sp, \offset
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.endm
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.macro cfi_restore reg offset=0 docfi=0
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.if \docfi
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.cfi_restore \reg
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.endif
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.endm
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.macro cfi_ld reg offset=0 docfi=0
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LONG_L \reg, sp, \offset
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cfi_restore \reg \offset \docfi
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.endm
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.macro SETUP_TWINS temp
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pcaddi t0, 0
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PTR_LI t1, ~TO_PHYS_MASK
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and t0, t0, t1
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ori t0, t0, (1 << 4 | 1)
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csrwr t0, LOONGARCH_CSR_DMWIN0
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PTR_LI t0, CSR_DMW1_INIT
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csrwr t0, LOONGARCH_CSR_DMWIN1
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.endm
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.macro SETUP_MODES temp
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/* Enable PG */
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li.w \temp, 0xb0 # PLV=0, IE=0, PG=1
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csrwr \temp, LOONGARCH_CSR_CRMD
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li.w \temp, 0x04 # PLV=0, PIE=1, PWE=0
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csrwr \temp, LOONGARCH_CSR_PRMD
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li.w \temp, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0
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csrwr \temp, LOONGARCH_CSR_EUEN
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.endm
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.macro SETUP_DMWINS temp
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PTR_LI \temp, CSR_DMW0_INIT # SUC, PLV0, LA32: 0x8xxx xxxx, LA64: 0x8000 xxxx xxxx xxxx
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csrwr \temp, LOONGARCH_CSR_DMWIN0
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PTR_LI \temp, CSR_DMW1_INIT # CAC, PLV0, LA32: 0xaxxx xxxx, LA64: 0x9000 xxxx xxxx xxxx
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csrwr \temp, LOONGARCH_CSR_DMWIN1
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PTR_LI \temp, CSR_DMW2_INIT # WUC, PLV0, LA32: unavailable, LA64: 0xa000 xxxx xxxx xxxx
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csrwr \temp, LOONGARCH_CSR_DMWIN2
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PTR_LI \temp, CSR_DMW3_INIT # 0x0, unused
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csrwr \temp, LOONGARCH_CSR_DMWIN3
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.endm
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/* Jump to the runtime virtual address. */
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.macro JUMP_VIRT_ADDR temp1 temp2
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PTR_LI \temp1, CACHE_BASE
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pcaddi \temp2, 0
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PTR_BSTRINS \temp1, \temp2, (DMW_PABITS - 1), 0
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jirl zero, \temp1, 0xc
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.endm
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.macro STACKLEAK_ERASE
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#ifdef CONFIG_KSTACK_ERASE
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bl stackleak_erase_on_task_stack
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#endif
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.endm
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.macro BACKUP_T0T1
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csrwr t0, EXCEPTION_KS0
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csrwr t1, EXCEPTION_KS1
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.endm
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.macro RELOAD_T0T1
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csrrd t0, EXCEPTION_KS0
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csrrd t1, EXCEPTION_KS1
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.endm
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.macro SAVE_TEMP docfi=0
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RELOAD_T0T1
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cfi_st t0, PT_R12, \docfi
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cfi_st t1, PT_R13, \docfi
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cfi_st t2, PT_R14, \docfi
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cfi_st t3, PT_R15, \docfi
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cfi_st t4, PT_R16, \docfi
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cfi_st t5, PT_R17, \docfi
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cfi_st t6, PT_R18, \docfi
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cfi_st t7, PT_R19, \docfi
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cfi_st t8, PT_R20, \docfi
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.endm
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.macro SAVE_STATIC docfi=0
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cfi_st s0, PT_R23, \docfi
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cfi_st s1, PT_R24, \docfi
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cfi_st s2, PT_R25, \docfi
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cfi_st s3, PT_R26, \docfi
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cfi_st s4, PT_R27, \docfi
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cfi_st s5, PT_R28, \docfi
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cfi_st s6, PT_R29, \docfi
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cfi_st s7, PT_R30, \docfi
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cfi_st s8, PT_R31, \docfi
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.endm
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/*
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* get_saved_sp returns the SP for the current CPU by looking in the
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* kernelsp array for it. It stores the current sp in t0 and loads the
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* new value in sp.
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*/
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.macro get_saved_sp docfi=0
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la_abs t1, kernelsp
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#ifdef CONFIG_SMP
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csrrd t0, PERCPU_BASE_KS
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LONG_ADD t1, t1, t0
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#endif
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move t0, sp
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.if \docfi
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.cfi_register sp, t0
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.endif
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LONG_L sp, t1, 0
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.endm
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.macro set_saved_sp stackp temp temp2
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la.pcrel \temp, kernelsp
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#ifdef CONFIG_SMP
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LONG_ADD \temp, \temp, u0
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#endif
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LONG_S \stackp, \temp, 0
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.endm
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.macro SAVE_SOME docfi=0
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csrrd t1, LOONGARCH_CSR_PRMD
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andi t1, t1, 0x3 /* extract pplv bit */
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move t0, sp
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beqz t1, 8f
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/* Called from user mode, new stack. */
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get_saved_sp docfi=\docfi
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8:
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PTR_ADDI sp, sp, -PT_SIZE
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.if \docfi
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.cfi_def_cfa sp, 0
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.endif
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cfi_st t0, PT_R3, \docfi
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cfi_rel_offset sp, PT_R3, \docfi
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LONG_S zero, sp, PT_R0
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csrrd t0, LOONGARCH_CSR_PRMD
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LONG_S t0, sp, PT_PRMD
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csrrd t0, LOONGARCH_CSR_CRMD
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LONG_S t0, sp, PT_CRMD
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csrrd t0, LOONGARCH_CSR_EUEN
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LONG_S t0, sp, PT_EUEN
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csrrd t0, LOONGARCH_CSR_ECFG
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LONG_S t0, sp, PT_ECFG
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csrrd t0, LOONGARCH_CSR_ESTAT
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PTR_S t0, sp, PT_ESTAT
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cfi_st ra, PT_R1, \docfi
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cfi_st a0, PT_R4, \docfi
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cfi_st a1, PT_R5, \docfi
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cfi_st a2, PT_R6, \docfi
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cfi_st a3, PT_R7, \docfi
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cfi_st a4, PT_R8, \docfi
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cfi_st a5, PT_R9, \docfi
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cfi_st a6, PT_R10, \docfi
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cfi_st a7, PT_R11, \docfi
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csrrd ra, LOONGARCH_CSR_ERA
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LONG_S ra, sp, PT_ERA
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.if \docfi
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.cfi_rel_offset ra, PT_ERA
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.endif
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cfi_st tp, PT_R2, \docfi
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cfi_st u0, PT_R21, \docfi
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cfi_st fp, PT_R22, \docfi
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/* Set thread_info if we're coming from user mode */
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csrrd t0, LOONGARCH_CSR_PRMD
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andi t0, t0, 0x3 /* extract pplv bit */
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beqz t0, 9f
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csrrd u0, PERCPU_BASE_KS
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la_abs t1, cpu_tasks
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#ifdef CONFIG_SMP
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LONG_ADD t1, t1, u0
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#endif
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LONG_L tp, t1, 0
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9:
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#ifdef CONFIG_KGDB
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li.w t0, CSR_CRMD_WE
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csrxchg t0, t0, LOONGARCH_CSR_CRMD
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#endif
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UNWIND_HINT_REGS
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.endm
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.macro SAVE_ALL docfi=0
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SAVE_SOME \docfi
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SAVE_TEMP \docfi
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SAVE_STATIC \docfi
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.endm
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.macro RESTORE_TEMP docfi=0
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cfi_ld t0, PT_R12, \docfi
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cfi_ld t1, PT_R13, \docfi
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cfi_ld t2, PT_R14, \docfi
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cfi_ld t3, PT_R15, \docfi
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cfi_ld t4, PT_R16, \docfi
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cfi_ld t5, PT_R17, \docfi
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cfi_ld t6, PT_R18, \docfi
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cfi_ld t7, PT_R19, \docfi
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cfi_ld t8, PT_R20, \docfi
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.endm
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.macro RESTORE_STATIC docfi=0
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cfi_ld s0, PT_R23, \docfi
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cfi_ld s1, PT_R24, \docfi
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cfi_ld s2, PT_R25, \docfi
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cfi_ld s3, PT_R26, \docfi
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cfi_ld s4, PT_R27, \docfi
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cfi_ld s5, PT_R28, \docfi
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cfi_ld s6, PT_R29, \docfi
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cfi_ld s7, PT_R30, \docfi
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cfi_ld s8, PT_R31, \docfi
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.endm
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.macro RESTORE_SOME docfi=0
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LONG_L a0, sp, PT_PRMD
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andi a0, a0, 0x3 /* extract pplv bit */
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beqz a0, 8f
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cfi_ld u0, PT_R21, \docfi
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8:
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LONG_L a0, sp, PT_ERA
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csrwr a0, LOONGARCH_CSR_ERA
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LONG_L a0, sp, PT_PRMD
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csrwr a0, LOONGARCH_CSR_PRMD
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cfi_ld ra, PT_R1, \docfi
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cfi_ld a0, PT_R4, \docfi
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cfi_ld a1, PT_R5, \docfi
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cfi_ld a2, PT_R6, \docfi
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cfi_ld a3, PT_R7, \docfi
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cfi_ld a4, PT_R8, \docfi
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cfi_ld a5, PT_R9, \docfi
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cfi_ld a6, PT_R10, \docfi
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cfi_ld a7, PT_R11, \docfi
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cfi_ld tp, PT_R2, \docfi
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cfi_ld fp, PT_R22, \docfi
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.endm
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.macro RESTORE_SP_AND_RET docfi=0
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cfi_ld sp, PT_R3, \docfi
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UNWIND_HINT_FUNC
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ertn
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.endm
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.macro RESTORE_ALL_AND_RET docfi=0
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RESTORE_STATIC \docfi
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RESTORE_TEMP \docfi
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RESTORE_SOME \docfi
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RESTORE_SP_AND_RET \docfi
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.endm
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#endif /* _ASM_STACKFRAME_H */
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