mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2026-08-14 06:22:34 +02:00
Kaustabh Chakraborty
e491ebea15
Samsung's S2MU005 PMIC includes subdevices for a charger, an MUIC (Micro USB Interface Controller), and flash and RGB LED controllers. S2MU005's interrupt registers divided into three domains, each for the charger, flash LEDs, and the MUIC, packed into a single regmap IRQ chip construct. In devices other than S2MPG1X, the revision can be retrieved from the first register of the PMIC regmap. In S2MU005 however, the location is in offset 0x73. Introduce a switch-case block to allow selecting the REG_ID register. S2MU005 also has a field mask for the revision. Apply it using FIELD_GET() and get the extracted value. Add initial support for S2MU005 in the PMIC driver, along with its three interrupt chips, and support for allowing to fetch revision based on the device variant. Co-developed-by: Łukasz Lebiedziński <kernel@lvkasz.us> Signed-off-by: Łukasz Lebiedziński <kernel@lvkasz.us> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Link: https://patch.msgid.link/20260516-s2mu005-pmic-v7-4-73f9702fb461@disroot.org Signed-off-by: Lee Jones <lee@kernel.org>
522 lines
14 KiB
C
522 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*/
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#ifndef __LINUX_MFD_SEC_IRQ_H
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#define __LINUX_MFD_SEC_IRQ_H
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enum s2mpa01_irq {
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S2MPA01_IRQ_PWRONF,
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S2MPA01_IRQ_PWRONR,
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S2MPA01_IRQ_JIGONBF,
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S2MPA01_IRQ_JIGONBR,
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S2MPA01_IRQ_ACOKBF,
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S2MPA01_IRQ_ACOKBR,
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S2MPA01_IRQ_PWRON1S,
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S2MPA01_IRQ_MRB,
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S2MPA01_IRQ_RTC60S,
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S2MPA01_IRQ_RTCA1,
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S2MPA01_IRQ_RTCA0,
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S2MPA01_IRQ_SMPL,
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S2MPA01_IRQ_RTC1S,
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S2MPA01_IRQ_WTSR,
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S2MPA01_IRQ_INT120C,
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S2MPA01_IRQ_INT140C,
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S2MPA01_IRQ_LDO3_TSD,
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S2MPA01_IRQ_B16_TSD,
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S2MPA01_IRQ_B24_TSD,
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S2MPA01_IRQ_B35_TSD,
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S2MPA01_IRQ_NR,
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};
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#define S2MPA01_IRQ_PWRONF_MASK (1 << 0)
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#define S2MPA01_IRQ_PWRONR_MASK (1 << 1)
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#define S2MPA01_IRQ_JIGONBF_MASK (1 << 2)
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#define S2MPA01_IRQ_JIGONBR_MASK (1 << 3)
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#define S2MPA01_IRQ_ACOKBF_MASK (1 << 4)
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#define S2MPA01_IRQ_ACOKBR_MASK (1 << 5)
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#define S2MPA01_IRQ_PWRON1S_MASK (1 << 6)
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#define S2MPA01_IRQ_MRB_MASK (1 << 7)
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#define S2MPA01_IRQ_RTC60S_MASK (1 << 0)
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#define S2MPA01_IRQ_RTCA1_MASK (1 << 1)
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#define S2MPA01_IRQ_RTCA0_MASK (1 << 2)
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#define S2MPA01_IRQ_SMPL_MASK (1 << 3)
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#define S2MPA01_IRQ_RTC1S_MASK (1 << 4)
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#define S2MPA01_IRQ_WTSR_MASK (1 << 5)
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#define S2MPA01_IRQ_INT120C_MASK (1 << 0)
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#define S2MPA01_IRQ_INT140C_MASK (1 << 1)
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#define S2MPA01_IRQ_LDO3_TSD_MASK (1 << 2)
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#define S2MPA01_IRQ_B16_TSD_MASK (1 << 3)
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#define S2MPA01_IRQ_B24_TSD_MASK (1 << 4)
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#define S2MPA01_IRQ_B35_TSD_MASK (1 << 5)
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enum s2mpg10_common_irq {
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/* Top-level (common) block */
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S2MPG10_COMMON_IRQ_PMIC,
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S2MPG10_COMMON_IRQ_UNUSED,
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};
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enum s2mpg10_irq {
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/* PMIC */
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S2MPG10_IRQ_PWRONF,
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S2MPG10_IRQ_PWRONR,
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S2MPG10_IRQ_JIGONBF,
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S2MPG10_IRQ_JIGONBR,
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S2MPG10_IRQ_ACOKBF,
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S2MPG10_IRQ_ACOKBR,
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S2MPG10_IRQ_PWRON1S,
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S2MPG10_IRQ_MRB,
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#define S2MPG10_IRQ_PWRONF_MASK BIT(0)
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#define S2MPG10_IRQ_PWRONR_MASK BIT(1)
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#define S2MPG10_IRQ_JIGONBF_MASK BIT(2)
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#define S2MPG10_IRQ_JIGONBR_MASK BIT(3)
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#define S2MPG10_IRQ_ACOKBF_MASK BIT(4)
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#define S2MPG10_IRQ_ACOKBR_MASK BIT(5)
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#define S2MPG10_IRQ_PWRON1S_MASK BIT(6)
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#define S2MPG10_IRQ_MRB_MASK BIT(7)
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S2MPG10_IRQ_RTC60S,
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S2MPG10_IRQ_RTCA1,
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S2MPG10_IRQ_RTCA0,
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S2MPG10_IRQ_RTC1S,
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S2MPG10_IRQ_WTSR_COLDRST,
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S2MPG10_IRQ_WTSR,
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S2MPG10_IRQ_WRST,
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S2MPG10_IRQ_SMPL,
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#define S2MPG10_IRQ_RTC60S_MASK BIT(0)
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#define S2MPG10_IRQ_RTCA1_MASK BIT(1)
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#define S2MPG10_IRQ_RTCA0_MASK BIT(2)
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#define S2MPG10_IRQ_RTC1S_MASK BIT(3)
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#define S2MPG10_IRQ_WTSR_COLDRST_MASK BIT(4)
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#define S2MPG10_IRQ_WTSR_MASK BIT(5)
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#define S2MPG10_IRQ_WRST_MASK BIT(6)
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#define S2MPG10_IRQ_SMPL_MASK BIT(7)
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S2MPG10_IRQ_120C,
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S2MPG10_IRQ_140C,
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S2MPG10_IRQ_TSD,
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S2MPG10_IRQ_PIF_TIMEOUT1,
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S2MPG10_IRQ_PIF_TIMEOUT2,
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S2MPG10_IRQ_SPD_PARITY_ERR,
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S2MPG10_IRQ_SPD_ABNORMAL_STOP,
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S2MPG10_IRQ_PMETER_OVERF,
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#define S2MPG10_IRQ_INT120C_MASK BIT(0)
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#define S2MPG10_IRQ_INT140C_MASK BIT(1)
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#define S2MPG10_IRQ_TSD_MASK BIT(2)
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#define S2MPG10_IRQ_PIF_TIMEOUT1_MASK BIT(3)
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#define S2MPG10_IRQ_PIF_TIMEOUT2_MASK BIT(4)
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#define S2MPG10_IRQ_SPD_PARITY_ERR_MASK BIT(5)
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#define S2MPG10_IRQ_SPD_ABNORMAL_STOP_MASK BIT(6)
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#define S2MPG10_IRQ_PMETER_OVERF_MASK BIT(7)
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S2MPG10_IRQ_OCP_B1M,
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S2MPG10_IRQ_OCP_B2M,
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S2MPG10_IRQ_OCP_B3M,
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S2MPG10_IRQ_OCP_B4M,
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S2MPG10_IRQ_OCP_B5M,
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S2MPG10_IRQ_OCP_B6M,
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S2MPG10_IRQ_OCP_B7M,
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S2MPG10_IRQ_OCP_B8M,
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#define S2MPG10_IRQ_OCP_B1M_MASK BIT(0)
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#define S2MPG10_IRQ_OCP_B2M_MASK BIT(1)
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#define S2MPG10_IRQ_OCP_B3M_MASK BIT(2)
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#define S2MPG10_IRQ_OCP_B4M_MASK BIT(3)
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#define S2MPG10_IRQ_OCP_B5M_MASK BIT(4)
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#define S2MPG10_IRQ_OCP_B6M_MASK BIT(5)
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#define S2MPG10_IRQ_OCP_B7M_MASK BIT(6)
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#define S2MPG10_IRQ_OCP_B8M_MASK BIT(7)
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S2MPG10_IRQ_OCP_B9M,
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S2MPG10_IRQ_OCP_B10M,
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S2MPG10_IRQ_WLWP_ACC,
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S2MPG10_IRQ_SMPL_TIMEOUT,
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S2MPG10_IRQ_WTSR_TIMEOUT,
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S2MPG10_IRQ_SPD_SRP_PKT_RST,
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#define S2MPG10_IRQ_OCP_B9M_MASK BIT(0)
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#define S2MPG10_IRQ_OCP_B10M_MASK BIT(1)
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#define S2MPG10_IRQ_WLWP_ACC_MASK BIT(2)
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#define S2MPG10_IRQ_SMPL_TIMEOUT_MASK BIT(5)
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#define S2MPG10_IRQ_WTSR_TIMEOUT_MASK BIT(6)
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#define S2MPG10_IRQ_SPD_SRP_PKT_RST_MASK BIT(7)
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S2MPG10_IRQ_PWR_WARN_CH0,
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S2MPG10_IRQ_PWR_WARN_CH1,
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S2MPG10_IRQ_PWR_WARN_CH2,
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S2MPG10_IRQ_PWR_WARN_CH3,
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S2MPG10_IRQ_PWR_WARN_CH4,
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S2MPG10_IRQ_PWR_WARN_CH5,
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S2MPG10_IRQ_PWR_WARN_CH6,
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S2MPG10_IRQ_PWR_WARN_CH7,
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#define S2MPG10_IRQ_PWR_WARN_CH0_MASK BIT(0)
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#define S2MPG10_IRQ_PWR_WARN_CH1_MASK BIT(1)
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#define S2MPG10_IRQ_PWR_WARN_CH2_MASK BIT(2)
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#define S2MPG10_IRQ_PWR_WARN_CH3_MASK BIT(3)
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#define S2MPG10_IRQ_PWR_WARN_CH4_MASK BIT(4)
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#define S2MPG10_IRQ_PWR_WARN_CH5_MASK BIT(5)
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#define S2MPG10_IRQ_PWR_WARN_CH6_MASK BIT(6)
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#define S2MPG10_IRQ_PWR_WARN_CH7_MASK BIT(7)
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S2MPG10_IRQ_NR,
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};
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enum s2mpg11_common_irq {
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/* Top-level (common) block */
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S2MPG11_COMMON_IRQ_PMIC,
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S2MPG11_COMMON_IRQ_UNUSED,
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};
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enum s2mpg11_irq {
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/* PMIC */
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S2MPG11_IRQ_PWRONF,
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S2MPG11_IRQ_PWRONR,
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S2MPG11_IRQ_PIF_TIMEOUT_MIF,
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S2MPG11_IRQ_PIF_TIMEOUTS,
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S2MPG11_IRQ_WTSR,
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S2MPG11_IRQ_SPD_ABNORMAL_STOP,
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S2MPG11_IRQ_SPD_PARITY_ERR,
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#define S2MPG11_IRQ_PWRONF_MASK BIT(0)
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#define S2MPG11_IRQ_PWRONR_MASK BIT(1)
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#define S2MPG11_IRQ_PIF_TIMEOUT_MIF_MASK BIT(3)
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#define S2MPG11_IRQ_PIF_TIMEOUTS_MASK BIT(4)
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#define S2MPG11_IRQ_WTSR_MASK BIT(5)
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#define S2MPG11_IRQ_SPD_ABNORMAL_STOP_MASK BIT(6)
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#define S2MPG11_IRQ_SPD_PARITY_ERR_MASK BIT(7)
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S2MPG11_IRQ_140C,
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S2MPG11_IRQ_120C,
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S2MPG11_IRQ_TSD,
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S2MPG11_IRQ_WRST,
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S2MPG11_IRQ_NTC_CYCLE_DONE,
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S2MPG11_IRQ_PMETER_OVERF,
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#define S2MPG11_IRQ_INT140C_MASK BIT(0)
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#define S2MPG11_IRQ_INT120C_MASK BIT(1)
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#define S2MPG11_IRQ_TSD_MASK BIT(2)
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#define S2MPG11_IRQ_WRST_MASK BIT(5)
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#define S2MPG11_IRQ_NTC_CYCLE_DONE_MASK BIT(6)
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#define S2MPG11_IRQ_PMETER_OVERF_MASK BIT(7)
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S2MPG11_IRQ_OCP_B1S,
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S2MPG11_IRQ_OCP_B2S,
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S2MPG11_IRQ_OCP_B3S,
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S2MPG11_IRQ_OCP_B4S,
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S2MPG11_IRQ_OCP_B5S,
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S2MPG11_IRQ_OCP_B6S,
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S2MPG11_IRQ_OCP_B7S,
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S2MPG11_IRQ_OCP_B8S,
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#define S2MPG11_IRQ_OCP_B1S_MASK BIT(0)
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#define S2MPG11_IRQ_OCP_B2S_MASK BIT(1)
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#define S2MPG11_IRQ_OCP_B3S_MASK BIT(2)
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#define S2MPG11_IRQ_OCP_B4S_MASK BIT(3)
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#define S2MPG11_IRQ_OCP_B5S_MASK BIT(4)
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#define S2MPG11_IRQ_OCP_B6S_MASK BIT(5)
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#define S2MPG11_IRQ_OCP_B7S_MASK BIT(6)
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#define S2MPG11_IRQ_OCP_B8S_MASK BIT(7)
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S2MPG11_IRQ_OCP_B9S,
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S2MPG11_IRQ_OCP_B10S,
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S2MPG11_IRQ_OCP_BDS,
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S2MPG11_IRQ_OCP_BAS,
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S2MPG11_IRQ_OCP_BBS,
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S2MPG11_IRQ_WLWP_ACC,
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S2MPG11_IRQ_SPD_SRP_PKT_RST,
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#define S2MPG11_IRQ_OCP_B9S_MASK BIT(0)
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#define S2MPG11_IRQ_OCP_B10S_MASK BIT(1)
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#define S2MPG11_IRQ_OCP_BDS_MASK BIT(2)
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#define S2MPG11_IRQ_OCP_BAS_MASK BIT(3)
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#define S2MPG11_IRQ_OCP_BBS_MASK BIT(4)
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#define S2MPG11_IRQ_WLWP_ACC_MASK BIT(5)
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#define S2MPG11_IRQ_SPD_SRP_PKT_RST_MASK BIT(7)
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S2MPG11_IRQ_PWR_WARN_CH0,
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S2MPG11_IRQ_PWR_WARN_CH1,
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S2MPG11_IRQ_PWR_WARN_CH2,
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S2MPG11_IRQ_PWR_WARN_CH3,
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S2MPG11_IRQ_PWR_WARN_CH4,
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S2MPG11_IRQ_PWR_WARN_CH5,
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S2MPG11_IRQ_PWR_WARN_CH6,
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S2MPG11_IRQ_PWR_WARN_CH7,
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#define S2MPG11_IRQ_PWR_WARN_CH0_MASK BIT(0)
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#define S2MPG11_IRQ_PWR_WARN_CH1_MASK BIT(1)
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#define S2MPG11_IRQ_PWR_WARN_CH2_MASK BIT(2)
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#define S2MPG11_IRQ_PWR_WARN_CH3_MASK BIT(3)
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#define S2MPG11_IRQ_PWR_WARN_CH4_MASK BIT(4)
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#define S2MPG11_IRQ_PWR_WARN_CH5_MASK BIT(5)
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#define S2MPG11_IRQ_PWR_WARN_CH6_MASK BIT(6)
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#define S2MPG11_IRQ_PWR_WARN_CH7_MASK BIT(7)
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S2MPG11_IRQ_NTC_WARN_CH0,
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S2MPG11_IRQ_NTC_WARN_CH1,
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S2MPG11_IRQ_NTC_WARN_CH2,
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S2MPG11_IRQ_NTC_WARN_CH3,
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S2MPG11_IRQ_NTC_WARN_CH4,
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S2MPG11_IRQ_NTC_WARN_CH5,
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S2MPG11_IRQ_NTC_WARN_CH6,
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S2MPG11_IRQ_NTC_WARN_CH7,
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#define S2MPG11_IRQ_NTC_WARN_CH0_MASK BIT(0)
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#define S2MPG11_IRQ_NTC_WARN_CH1_MASK BIT(1)
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#define S2MPG11_IRQ_NTC_WARN_CH2_MASK BIT(2)
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#define S2MPG11_IRQ_NTC_WARN_CH3_MASK BIT(3)
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#define S2MPG11_IRQ_NTC_WARN_CH4_MASK BIT(4)
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#define S2MPG11_IRQ_NTC_WARN_CH5_MASK BIT(5)
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#define S2MPG11_IRQ_NTC_WARN_CH6_MASK BIT(6)
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#define S2MPG11_IRQ_NTC_WARN_CH7_MASK BIT(7)
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S2MPG11_IRQ_NR,
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};
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enum s2mps11_irq {
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S2MPS11_IRQ_PWRONF,
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S2MPS11_IRQ_PWRONR,
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S2MPS11_IRQ_JIGONBF,
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S2MPS11_IRQ_JIGONBR,
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S2MPS11_IRQ_ACOKBF,
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S2MPS11_IRQ_ACOKBR,
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S2MPS11_IRQ_PWRON1S,
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S2MPS11_IRQ_MRB,
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S2MPS11_IRQ_RTC60S,
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S2MPS11_IRQ_RTCA1,
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S2MPS11_IRQ_RTCA0,
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S2MPS11_IRQ_SMPL,
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S2MPS11_IRQ_RTC1S,
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S2MPS11_IRQ_WTSR,
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S2MPS11_IRQ_INT120C,
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S2MPS11_IRQ_INT140C,
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S2MPS11_IRQ_NR,
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};
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#define S2MPS11_IRQ_PWRONF_MASK (1 << 0)
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#define S2MPS11_IRQ_PWRONR_MASK (1 << 1)
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#define S2MPS11_IRQ_JIGONBF_MASK (1 << 2)
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#define S2MPS11_IRQ_JIGONBR_MASK (1 << 3)
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#define S2MPS11_IRQ_ACOKBF_MASK (1 << 4)
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#define S2MPS11_IRQ_ACOKBR_MASK (1 << 5)
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#define S2MPS11_IRQ_PWRON1S_MASK (1 << 6)
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#define S2MPS11_IRQ_MRB_MASK (1 << 7)
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#define S2MPS11_IRQ_RTC60S_MASK (1 << 0)
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#define S2MPS11_IRQ_RTCA1_MASK (1 << 1)
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#define S2MPS11_IRQ_RTCA0_MASK (1 << 2)
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#define S2MPS11_IRQ_SMPL_MASK (1 << 3)
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#define S2MPS11_IRQ_RTC1S_MASK (1 << 4)
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#define S2MPS11_IRQ_WTSR_MASK (1 << 5)
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#define S2MPS11_IRQ_INT120C_MASK (1 << 0)
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#define S2MPS11_IRQ_INT140C_MASK (1 << 1)
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enum s2mps14_irq {
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S2MPS14_IRQ_PWRONF,
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S2MPS14_IRQ_PWRONR,
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S2MPS14_IRQ_JIGONBF,
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S2MPS14_IRQ_JIGONBR,
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S2MPS14_IRQ_ACOKBF,
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S2MPS14_IRQ_ACOKBR,
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S2MPS14_IRQ_PWRON1S,
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S2MPS14_IRQ_MRB,
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S2MPS14_IRQ_RTC60S,
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S2MPS14_IRQ_RTCA1,
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S2MPS14_IRQ_RTCA0,
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S2MPS14_IRQ_SMPL,
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S2MPS14_IRQ_RTC1S,
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S2MPS14_IRQ_WTSR,
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S2MPS14_IRQ_INT120C,
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S2MPS14_IRQ_INT140C,
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S2MPS14_IRQ_TSD,
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S2MPS14_IRQ_NR,
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};
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enum s2mpu02_irq {
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S2MPU02_IRQ_PWRONF,
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S2MPU02_IRQ_PWRONR,
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S2MPU02_IRQ_JIGONBF,
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S2MPU02_IRQ_JIGONBR,
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S2MPU02_IRQ_ACOKBF,
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S2MPU02_IRQ_ACOKBR,
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S2MPU02_IRQ_PWRON1S,
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S2MPU02_IRQ_MRB,
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S2MPU02_IRQ_RTC60S,
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S2MPU02_IRQ_RTCA1,
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S2MPU02_IRQ_RTCA0,
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S2MPU02_IRQ_SMPL,
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S2MPU02_IRQ_RTC1S,
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S2MPU02_IRQ_WTSR,
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S2MPU02_IRQ_INT120C,
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S2MPU02_IRQ_INT140C,
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S2MPU02_IRQ_TSD,
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S2MPU02_IRQ_NR,
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};
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/* Masks for interrupts are the same as in s2mps11 */
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#define S2MPS14_IRQ_TSD_MASK (1 << 2)
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enum s2mpu05_irq {
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S2MPU05_IRQ_PWRONF,
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S2MPU05_IRQ_PWRONR,
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S2MPU05_IRQ_JIGONBF,
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S2MPU05_IRQ_JIGONBR,
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S2MPU05_IRQ_ACOKF,
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S2MPU05_IRQ_ACOKR,
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S2MPU05_IRQ_PWRON1S,
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S2MPU05_IRQ_MRB,
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S2MPU05_IRQ_RTC60S,
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S2MPU05_IRQ_RTCA1,
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S2MPU05_IRQ_RTCA0,
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S2MPU05_IRQ_SMPL,
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S2MPU05_IRQ_RTC1S,
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S2MPU05_IRQ_WTSR,
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|
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S2MPU05_IRQ_INT120C,
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S2MPU05_IRQ_INT140C,
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S2MPU05_IRQ_TSD,
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|
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S2MPU05_IRQ_NR,
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};
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#define S2MPU05_IRQ_PWRONF_MASK BIT(0)
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#define S2MPU05_IRQ_PWRONR_MASK BIT(1)
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#define S2MPU05_IRQ_JIGONBF_MASK BIT(2)
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#define S2MPU05_IRQ_JIGONBR_MASK BIT(3)
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#define S2MPU05_IRQ_ACOKF_MASK BIT(4)
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#define S2MPU05_IRQ_ACOKR_MASK BIT(5)
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#define S2MPU05_IRQ_PWRON1S_MASK BIT(6)
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|
#define S2MPU05_IRQ_MRB_MASK BIT(7)
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|
|
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#define S2MPU05_IRQ_RTC60S_MASK BIT(0)
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|
#define S2MPU05_IRQ_RTCA1_MASK BIT(1)
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|
#define S2MPU05_IRQ_RTCA0_MASK BIT(2)
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|
#define S2MPU05_IRQ_SMPL_MASK BIT(3)
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|
#define S2MPU05_IRQ_RTC1S_MASK BIT(4)
|
|
#define S2MPU05_IRQ_WTSR_MASK BIT(5)
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|
|
|
#define S2MPU05_IRQ_INT120C_MASK BIT(0)
|
|
#define S2MPU05_IRQ_INT140C_MASK BIT(1)
|
|
#define S2MPU05_IRQ_TSD_MASK BIT(2)
|
|
|
|
enum s2mu005_irq {
|
|
S2MU005_IRQ_CHGR_DETBAT,
|
|
S2MU005_IRQ_CHGR_BAT,
|
|
S2MU005_IRQ_CHGR_IVR,
|
|
S2MU005_IRQ_CHGR_EVENT,
|
|
S2MU005_IRQ_CHGR_CHG,
|
|
S2MU005_IRQ_CHGR_VMID,
|
|
S2MU005_IRQ_CHGR_WCIN,
|
|
S2MU005_IRQ_CHGR_VBUS,
|
|
|
|
S2MU005_IRQ_FLED_LBPROT,
|
|
S2MU005_IRQ_FLED_OPENCH2,
|
|
S2MU005_IRQ_FLED_OPENCH1,
|
|
S2MU005_IRQ_FLED_SHORTCH2,
|
|
S2MU005_IRQ_FLED_SHORTCH1,
|
|
|
|
S2MU005_IRQ_MUIC_ATTACH,
|
|
S2MU005_IRQ_MUIC_DETACH,
|
|
S2MU005_IRQ_MUIC_KP,
|
|
S2MU005_IRQ_MUIC_LKP,
|
|
S2MU005_IRQ_MUIC_LKR,
|
|
S2MU005_IRQ_MUIC_RIDCHG,
|
|
|
|
S2MU005_IRQ_MUIC_VBUSON,
|
|
S2MU005_IRQ_MUIC_RSVD,
|
|
S2MU005_IRQ_MUIC_ADC,
|
|
S2MU005_IRQ_MUIC_STUCK,
|
|
S2MU005_IRQ_MUIC_STUCKRCV,
|
|
S2MU005_IRQ_MUIC_MHDL,
|
|
S2MU005_IRQ_MUIC_AVCHG,
|
|
S2MU005_IRQ_MUIC_VBUSOFF,
|
|
|
|
S2MU005_IRQ_NR,
|
|
};
|
|
|
|
#define S2MU005_IRQ_CHGR_DETBAT_MASK BIT(0)
|
|
#define S2MU005_IRQ_CHGR_BAT_MASK BIT(1)
|
|
#define S2MU005_IRQ_CHGR_IVR_MASK BIT(2)
|
|
#define S2MU005_IRQ_CHGR_EVENT_MASK BIT(3)
|
|
#define S2MU005_IRQ_CHGR_CHG_MASK BIT(4)
|
|
#define S2MU005_IRQ_CHGR_VMID_MASK BIT(5)
|
|
#define S2MU005_IRQ_CHGR_WCIN_MASK BIT(6)
|
|
#define S2MU005_IRQ_CHGR_VBUS_MASK BIT(7)
|
|
|
|
#define S2MU005_IRQ_FLED_LBPROT_MASK BIT(2)
|
|
#define S2MU005_IRQ_FLED_OPENCH2_MASK BIT(4)
|
|
#define S2MU005_IRQ_FLED_OPENCH1_MASK BIT(5)
|
|
#define S2MU005_IRQ_FLED_SHORTCH2_MASK BIT(6)
|
|
#define S2MU005_IRQ_FLED_SHORTCH1_MASK BIT(7)
|
|
|
|
#define S2MU005_IRQ_MUIC_ATTACH_MASK BIT(0)
|
|
#define S2MU005_IRQ_MUIC_DETACH_MASK BIT(1)
|
|
#define S2MU005_IRQ_MUIC_KP_MASK BIT(2)
|
|
#define S2MU005_IRQ_MUIC_LKP_MASK BIT(3)
|
|
#define S2MU005_IRQ_MUIC_LKR_MASK BIT(4)
|
|
#define S2MU005_IRQ_MUIC_RIDCHG_MASK BIT(5)
|
|
|
|
#define S2MU005_IRQ_MUIC_VBUSON_MASK BIT(0)
|
|
#define S2MU005_IRQ_MUIC_RSVD_MASK BIT(1)
|
|
#define S2MU005_IRQ_MUIC_ADC_MASK BIT(2)
|
|
#define S2MU005_IRQ_MUIC_STUCK_MASK BIT(3)
|
|
#define S2MU005_IRQ_MUIC_STUCKRCV_MASK BIT(4)
|
|
#define S2MU005_IRQ_MUIC_MHDL_MASK BIT(5)
|
|
#define S2MU005_IRQ_MUIC_AVCHG_MASK BIT(6)
|
|
#define S2MU005_IRQ_MUIC_VBUSOFF_MASK BIT(7)
|
|
|
|
enum s5m8767_irq {
|
|
S5M8767_IRQ_PWRR,
|
|
S5M8767_IRQ_PWRF,
|
|
S5M8767_IRQ_PWR1S,
|
|
S5M8767_IRQ_JIGR,
|
|
S5M8767_IRQ_JIGF,
|
|
S5M8767_IRQ_LOWBAT2,
|
|
S5M8767_IRQ_LOWBAT1,
|
|
|
|
S5M8767_IRQ_MRB,
|
|
S5M8767_IRQ_DVSOK2,
|
|
S5M8767_IRQ_DVSOK3,
|
|
S5M8767_IRQ_DVSOK4,
|
|
|
|
S5M8767_IRQ_RTC60S,
|
|
S5M8767_IRQ_RTCA1,
|
|
S5M8767_IRQ_RTCA2,
|
|
S5M8767_IRQ_SMPL,
|
|
S5M8767_IRQ_RTC1S,
|
|
S5M8767_IRQ_WTSR,
|
|
|
|
S5M8767_IRQ_NR,
|
|
};
|
|
|
|
#define S5M8767_IRQ_PWRR_MASK (1 << 0)
|
|
#define S5M8767_IRQ_PWRF_MASK (1 << 1)
|
|
#define S5M8767_IRQ_PWR1S_MASK (1 << 3)
|
|
#define S5M8767_IRQ_JIGR_MASK (1 << 4)
|
|
#define S5M8767_IRQ_JIGF_MASK (1 << 5)
|
|
#define S5M8767_IRQ_LOWBAT2_MASK (1 << 6)
|
|
#define S5M8767_IRQ_LOWBAT1_MASK (1 << 7)
|
|
|
|
#define S5M8767_IRQ_MRB_MASK (1 << 2)
|
|
#define S5M8767_IRQ_DVSOK2_MASK (1 << 3)
|
|
#define S5M8767_IRQ_DVSOK3_MASK (1 << 4)
|
|
#define S5M8767_IRQ_DVSOK4_MASK (1 << 5)
|
|
|
|
#define S5M8767_IRQ_RTC60S_MASK (1 << 0)
|
|
#define S5M8767_IRQ_RTCA1_MASK (1 << 1)
|
|
#define S5M8767_IRQ_RTCA2_MASK (1 << 2)
|
|
#define S5M8767_IRQ_SMPL_MASK (1 << 3)
|
|
#define S5M8767_IRQ_RTC1S_MASK (1 << 4)
|
|
#define S5M8767_IRQ_WTSR_MASK (1 << 5)
|
|
|
|
#endif /* __LINUX_MFD_SEC_IRQ_H */
|