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David S. Miller
64e09d04b9
Yoshihiro Shimoda says: ==================== net: renesas: rswitch: Modify initialization for SERDES and PHY - My platform has the 88x2110. - The MACTYPE setting of strap pin on the platform is SXGMII. - However, we realized that the SoC cannot communicate the PHY with SXGMII because of mismatching hardware specification. - We have a lot of boards which mismatch the MACTYPE setting. So, I would like to change the MACTYPE as SGMII by software for the platform. The patch [1/5] sets phydev->host_interfaces by phylink for Marvell PHY driver (marvell10g) to initialize the MACTYPE. - The patch [1/5] siplifies the rswitch driver. - The patch [2/5] converts to phy_device from phylink. - The patch [3/5] sets phydev->host_interfaces from this driver without any new functions of phylib. - The patch [4/5] adds phy_power_on() calling to initialize the Ethernet SERDES PHY driver (r8a779f0-eth-serdes) for each channel. - The patch [5/5] adds "max-speed" handling. Changes from v4: https://lore.kernel.org/all/20230127142621.1761278-1-yoshihiro.shimoda.uh@renesas.com/ - No modification of phylink API. - Convert to phylib instead of phylink. - Add "max-speed" handling. Changes from v3: https://lore.kernel.org/all/20230127014812.1656340-1-yoshihiro.shimoda.uh@renesas.com/ - Keep a pointer of "port" and more simplify the code. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
Linux kernel
============
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