Stephen Boyd 6e11940ab3 Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner', 'clk-samsung' and 'clk-amlogic' into clk-next
- Make clk_ops::determine_rate mandatory for muxes

* clk-renesas:
  clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()
  clk: renesas: mstp: Convert to readl_poll_timeout_atomic()
  clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic()
  iopoll: Do not use timekeeping in read_poll_timeout_atomic()
  iopoll: Call cpu_relax() in busy loops
  clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write
  clk: renesas: r8a779a0: Add PWM clock

* clk-determine-rate: (71 commits)
  clk: sprd: composite: Simplify determine_rate implementation
  ASoC: tlv320aic32x4: pll: Remove impossible condition in clk_aic32x4_pll_determine_rate()
  clk: Fix best_parent_rate after moving code into a separate function
  clk: Forbid to register a mux without determine_rate
  ASoC: tlv320aic32x4: div: Switch to determine_rate
  ASoC: tlv320aic32x4: pll: Switch to determine_rate
  clk: tegra: super: Switch to determine_rate
  clk: tegra: periph: Switch to determine_rate
  clk: stm32: composite: Switch to determine_rate
  clk: st: flexgen: Switch to determine_rate
  clk: sprd: composite: Switch to determine_rate
  clk: ingenic: tcu: Switch to determine_rate
  clk: ingenic: cgu: Switch to determine_rate
  clk: imx: scu: Switch to determine_rate
  clk: da8xx: clk48: Switch to determine_rate
  clk: si5351: clkout: Switch to determine_rate
  clk: si5351: msynth: Switch to determine_rate
  clk: si5351: pll: Switch to determine_rate
  clk: si5341: Switch to determine_rate
  clk: cdce706: clkout: Switch to determine_rate
  ...

* clk-allwinner:
  clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux

* clk-samsung:
  clk: samsung: add CONFIG_OF dependency
  clk: samsung: Re-add support for Exynos4212 CPU clock
  clk: samsung: Add Exynos4212 compatible to CLKOUT driver
  dt-bindings: clock: samsung,exynos: add Exynos4212 clock compatible

* clk-amlogic:
  MAINTAINERS: repair pattern in ARM/Amlogic Meson SoC CLOCK FRAMEWORK
  clk: meson: pll: remove unneeded semicolon
  clk: meson: a1: Staticize rtc clk
  clk: meson: a1: add Amlogic A1 Peripherals clock controller driver
  clk: meson: a1: add Amlogic A1 PLL clock controller driver
  clk: meson: introduce new pll power-on sequence for A1 SoC family
  clk: meson: make pll rst bit as optional
  dt-bindings: clock: meson: add A1 Peripherals clock controller bindings
  dt-bindings: clock: meson: add A1 PLL clock controller bindings
2023-06-26 08:55:04 -07:00
2022-09-28 09:02:20 +02:00
…
…
2023-05-07 13:34:35 -07:00
…

Linux kernel
============

There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.

In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``.  The formatted documentation can also be read online at:

    https://www.kernel.org/doc/html/latest/

There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.

Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.
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