Sen Wang a6d0abb350 ASoC: tlv320aic3x: restrict CLKDIV bypass Q values in dual-rate mode
[ Upstream commit fdf043f5f3 ]

The datasheet documents that when the PLL is disabled and dual-rate mode
is enabled, only Q values {4, 8, 9, 12, 16} are valid for the CLKDIV
bypass path; all other Q values produce invalid bitclock output.

The existing loop iterates Q from 2 to 17 without this restriction,
causing silent audio failure when an out-of-spec Q is picked.

Restrict the Q search to the allowed set in dual-rate mode.

Fixes: 4f9c16ccfa ("[ALSA] soc - tlv320aic3x - revisit clock setup")
Suggested-by: Mir Jeffres <m-jeffres@ti.com>
Signed-off-by: Sen Wang <sen@ti.com>
Link: https://patch.msgid.link/20260616233322.873081-1-sen@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2026-07-24 16:03:18 +02:00
2026-07-24 16:03:06 +02:00
2026-05-23 13:03:09 +02:00
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2026-05-23 13:03:09 +02:00
2026-07-04 13:42:28 +02:00
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Linux kernel
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There are several guides for kernel developers and users. These guides can
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In order to build the documentation, use ``make htmldocs`` or
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    https://www.kernel.org/doc/html/latest/

There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.

Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.
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