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Kuninori Morimoto
bd4cee2fdf
Basically Renesas sound ADG is assuming that it has accurately divisible input clock. But sometimes / some board might not have it. The clk_i from CPG is used for such case. It can't calculate accurate division, but can be used as approximate rate. This patch enable clk_i for such case. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Adnan Ali <adnan.ali@bp.renesas.com> Tested-by: Vincenzo De Michele <vincenzo.michele@davinci.de> Tested-by: Patrick Keil <patrick.keil@conti-engineering.com> Link: https://lore.kernel.org/r/87msyizlfd.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
Linux kernel
============
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