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Harry Wentland
cafa53d327
commit76a2db58e9upstream. dcn32_update_clocks_update_dtb_dto() reprograms the DTB DTO of every timing generator in the context whenever the DTBCLK reference changes, passing a zeroed pixel rate and never setting is_hdmi. dccg32_set_dtbclk_dto() treats a zero pixel rate as a disable request, and that branch drives PIPE_DTO_SRC_SEL to the DP DTO source. A timing generator actively scanning out an HDMI stream therefore has its pixel rate source re-muxed out from under the live raster, and the OTG stops on the spot. Two displays where only one runs a 128b/132b link hit this reliably. is_dtbclk_required() holds the DTBCLK reference high while both are active, and the moment the 128b/132b stream is torn down (compositor switch, display disable, hot-unplug) the next safe_to_lower pass drops the reference to the lowest DPM level and the DTO walk freezes the surviving screen. On Navi31 the DAL mailbox then goes deaf on the DISPCLK hard-min that follows the walk in dcn32_update_clocks(), stranding both SMU mailboxes until reboot. Set is_hdmi for HDMI and DVI signals so the disable path leaves the pixel rate source selection on the HDMI path, and pass the real pixel rate for 128b/132b streams so a reference change rescales their DTO instead of disabling it. Fixes:128c1ca030("drm/amd/display: Update DTBCLK for DCN32") Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> [ mschwartz: dcn32 clk_mgr hunk only, as 6.6.y predates the dcn35 clk_mgr. The rest is HDMI FRL enablement, absent before 7.2, so the FRL conditions and the req_audio_dtbclk_khz assignment they guard are dropped and the FRL-centric changelog is rewritten. Added the pipe_ctx->stream check the new dereferences need. ] Signed-off-by: Matthew Schwartz <matthew.schwartz@linux.dev> Signed-off-by: Sasha Levin <sashal@kernel.org>