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c994282e62 · Enable Emscripten in LocalTestingDistributedActorSystem.swift (#87797) · Updated 2026-06-20 05:11:06 +02:00

Branches

9e6b6b1b0b · Merge remote-tracking branch 'origin/main' into rebranch · Updated 2026-06-20 05:15:25 +02:00

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c1f25208d0 · Merge remote-tracking branch 'origin/main' into next · Updated 2026-06-20 05:14:55 +02:00

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680e099825 · swift-xcodegen: Infer project root from build directory first · Updated 2026-06-20 03:49:51 +02:00

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fb5d4d3cdb · [RBI]: Don't suppress intra-actor sends when value is sending · Updated 2026-06-19 15:29:48 +02:00

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f07dfa54ce · Subtle bit of efficiency · Updated 2026-06-19 02:57:06 +02:00

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c8b0ebd92a · [CodeGen] Handle clang-target and codegen target in directCC1 mode · Updated 2026-06-19 00:42:32 +02:00

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8dc43c66ff · Switch course to support yXlD · Updated 2026-06-18 21:43:32 +02:00

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bbc4515fac · Merge pull request #89980 from a-viv-a/invalid-explicit-sendable-conformance-6.4 · Updated 2026-06-18 20:03:59 +02:00

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e546f128c0 · [AutoDiff] Allow more VJP inlining decisions · Updated 2026-06-18 16:55:51 +02:00

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54013de569 · [WIP][DNM]: try to fix some bad RBI error suppressions · Updated 2026-06-18 03:24:05 +02:00

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35689fdc76 · Fix diagnostic for @c enum T: Int128. · Updated 2026-06-17 20:47:42 +02:00

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c4786e32ff · [Dependency Scanning] ClangImporter: Adjust to "[clang][modules] Serialize CodeGenOptions (#146422)" · Updated 2026-06-17 20:35:01 +02:00

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ca64cc4e1f · Revert "Revert "[Concurrency] Async{Throwing}Stream state machine reimplement…" · Updated 2026-06-17 03:19:42 +02:00

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91ba7dd13f · Make async typed throws fix Wasm-only · Updated 2026-06-16 14:43:23 +02:00

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92199c0179 · Merge remote-tracking branch 'origin/main' into rebranch · Updated 2026-06-15 23:15:15 +02:00

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8f5ff3ca31 · [tests] Dynamically detect simulator device names instead of hardcoding · Updated 2026-06-12 06:59:36 +02:00

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c29db13bbf · Refactoring the code so the interface is a bit closer to what we want on the clang side. · Updated 2026-06-11 23:26:20 +02:00

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2e7a407e35 · Merge pull request #89693 from xedin/rdar-178397835-6.3 · Updated 2026-06-08 19:24:09 +02:00

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f6f046fec6 · Revert "IRGen: Switch LLVM pipeline optimization level from Os to O2" · Updated 2026-06-04 14:48:25 +02:00

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531c28a575 · Fix stray whitespace · Updated 2026-06-03 20:22:59 +02:00

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