Commit Graph

6 Commits

Author SHA1 Message Date
Tim Kientzle
1d961ba22d Add #include "swift/Basic/Assertions.h" to a lot of source files
Although I don't plan to bring over new assertions wholesale
into the current qualification branch, it's entirely possible
that various minor changes in main will use the new assertions;
having this basic support in the release branch will simplify that.
(This is why I'm adding the includes as a separate pass from
rewriting the individual assertions)
2024-06-05 19:37:30 -07:00
Emil Pedersen
35e346fd8d Add support for op_tuple_fragment in SIL DIExpression and SIL SROA
rdar://124034536
2024-03-04 15:46:02 -08:00
Josh Soref
d767912be2 Spelling sil (#42471)
* spelling: accessible

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* spelling: compatible

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* spelling: declarations

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* spelling: deserialization

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* spelling: determined

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* spelling: doesn't

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* spelling: equality

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* spelling: equivalent

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* spelling: formation

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* spelling: guaranteed

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* spelling: identify

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* spelling: inaccessible

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* spelling: indeterminate

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* spelling: indices

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* spelling: inefficient

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* spelling: inheritance

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* spelling: instruction

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* spelling: intentionally

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* spelling: interior

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* spelling: intrinsic

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* spelling: introducing

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* spelling: irrelevant

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* spelling: message

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* spelling: multi

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* spelling: object

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* spelling: one

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* spelling: optimization

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* spelling: otherwise

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* spelling: overridden

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* spelling: parameter

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* spelling: pattern

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* spelling: pipeline

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* spelling: possibility

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* spelling: postdominance

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* spelling: providing

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* spelling: resilient

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* spelling: retrieve

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* spelling: scavenge

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* spelling: separately

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* spelling: subtypes

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* spelling: supplement

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* spelling: syntax

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* spelling: transitively

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* spelling: trivial

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* spelling: value

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* spelling: verification

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* spelling: whole

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Co-authored-by: Josh Soref <jsoref@users.noreply.github.com>
2022-04-22 15:11:09 -07:00
Min-Yih Hsu
ece59c4718 (Stash) Add in-memory representation, parsing and printing 2021-09-10 14:17:38 -07:00
Min-Yih Hsu
9a8f2ed642 [SILOptimizer][DebugInfo] Preliminary support for DIExpression in SROA and Mem2Reg
SROA and Mem2Reg now can leverage DIExpression -- op_fragment, more
specifically -- to generate correct debug info for optimized SIL. Some
important highlights:
 - The new swift::salvageDebugInfo, similar to llvm::salvageDebugInfo,
   tries to restore / transfer debug info from a deleted instruction.
   Currently I only implemented this for store instruction whose
   destination is an alloc_stack value.
 - Since we now have source-variable-specific SIL location inside a
   `debug_value` instruction (and its friends), this patch teaches
   SILCloner and SILInliner to remap the debug scope there in addition
   to debug scope of the instruction.
 - DCE now does not remove `debug_value` instruction whose associating
   with a function argument SSA value that is not used elsewhere. Since
   that SSA value will not disappear so we should keep the debug info.
2021-08-05 17:27:45 -07:00
Min-Yih Hsu
377bdfaf12 [SIL][DebugInfo][Patch 1/2] Initial SIL DIExpression support
Currently the debug info infrastructure inside SIL can only associate a
source variable with a single (simple) SSA value. Which is insufficient
to preserve (correct) debug info across SIL-level optimizations -- for
example, SROA that decompose or even eliminate aggregate-type obejcts.

By adding DIExpression into SIL, we are able to reconstruct the
connection between a source variable and its SSA value counterpart, even
across optimizations. This patch adds such support into in-memory
representation for SIL instructions and the SILParser/Printer. The
following patch will add changes for the IRGen part.
2021-07-21 09:26:45 -07:00